DATASHEET 74LS90 PDF

All materials on our website are shared by users. If you have any questions about copyright issues, please report us to resolve them. We are always happy to assist you. Each section can be used separately or tied together Q to CP to form BCD, bi-quinary, modulo, or modulo counters. The Output LOW drive factor is 2. Temperature Ranges.

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All materials on our website are shared by users. If you have any questions about copyright issues, please report us to resolve them. We are always happy to assist you. Each section can be used separately or tied together Q to CP to form BCD, bi-quinary, modulo, or modulo counters. The Output LOW drive factor is 2.

Temperature Ranges. The Q0Outputs are guaranteed to drive the full fan-out plus the CP1input of the device. To insure proper operation the rise tr and fall time tf of the clock must be less than ns. State changes of the Q outputs do not occursimultaneously because of internal ripple delays. Therefore,decoded output signals are subject to decoding spikes andshould not be used for clocks or strobes. The Q0output ofeach device is designed and specified to drive the ratedfan-out plus the CP1input of the device.

Since the output from the divide-by-two section is notinternally connected to the succeeding stages, the devicesmay be operated in various counting modes. LS90 A. Theinput count is then applied to the CP1input and a divide-by-ten square wave is obtained at output Q0. The first flip-flop is used as abinary element for the divide-by-two function CP0as theinput and Q0as the output. The CP1input is used to obtainbinary divide-by-five operation at the Q3output.

LS92 A. The CP0in-put receives the incoming count and Q3produces a sym-metrical divide-by-twelve square wave output. The first flip-flop is used as abinary element for the divide-by-two function.

The CP1in-put is used to obtain divide-by-three operation at the Q1and Q2outputs and divide-by-six operation at the Q3out-put.

LS93 A. The input count pulses are appliedto input CP0. Simultaneous divisions of 2, 4, 8, and 16 areperformed at the Q0, Q1, Q2, and Q3outputs as shown inthe truth table. Simultaneous frequency divisions of 2, 4, and8 are available at the Q1, Q2, and Q3outputs. Independentuse of the first flip-flop is available if the reset function coin-cides with reset of the 3-bit ripple-through counter.

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